View ISL2231710_4554250.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL22317
Precision Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet April 15, 2010 FN6912.1
Low Noise, Low Power, I2CTM Bus, 128 Taps
The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR control the position of the wiper. At power up, the device recalls the contents of the DCP's IVR to the WR. The highly precise ISL22317 features a low end-to-end temperature coefficient of TC_Ref 10ppm/C and precise resistance selection. It maintains less than 1% typical variance from the ideal resistance at each wiper position providing 99% accuracy of selected resistance value. This highly accurate DCP eliminates the need for complex algorithms to guarantee precision. The ISL22317 allows the user to dial in an accurate resistance and the EEPROM memory stores the set value for life, or until changed by the user. An external 0.5% or better reference resistor must be attached to the ISL22317. The ISL22317 will mirror both the precise resistance and temperature coefficient of the external resistor. The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Precision Digitally Controlled Potentiometer - 99% Typical Accuracy Of Resistance Over Operational Conditions - Zero-Compensated Wiper Resistance * Integrated Digitally Controlled Potentiometer - 128-Tap Positions - I2C Serial Interface - Pin Selectable Slave Address - 10k, 50k and 100kTotal Resistance - Monotonic Over-Temperature - Non-Volatile EEPROM Storage of Wiper Position - 0 to VCC Terminal Voltage * Single 2.7V to 5.5V Supply * High Reliability - 50 Years Retention @ +55C - 15 Years Retention @ +125C - 1,000,000 Cycles Endurance * 3mmx3mm Thin DFN Package - 0.75mm Max Thickness, 0.65mm Pitch * Pb-Free (RoHS Compliant)
Applications
* Setting Precise Current Values for DC Margining and Backlight Control * Replaces Complex Compensation Circuitry That Stores Values in Look-up Tables Needed for Precise Resistor Setting * Setting Precise Resistance Values for Test and Measurement Circuits
Pinout
ISL22317 (10 LD TDFN) TOP VIEW
SCL SDA A1 REF_A REF_B 1 2 3 4 5 10 VCC 9 RH 8 RW 7 RL 6 GND
* Adjust Specific Resistances in Analog Circuits * Precise Calibration and Fine Tune-Up
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. 2C BusTM is a trademark owned by NXP Semiconductors Netherlands, B.V. Copyright Intersil Americas Inc. 2009, 2010. I All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL22317 Ordering Information
PART NUMBER (Notes 1, 2, 3) ISL22317TFRTZ ISL22317UFRTZ ISL22317WFRTZ NOTES: 1. Add "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL22317. For more information on MSL please see techbrief TB363. PART MARKING 317T 317U 317W RESISTANCE OPTION (k) 100 50 10 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-free) 10 Ld TDFN 10 Ld TDFN 10 Ld TDFN PKG. DWG. # L10.3x3B L10.3x3B L10.3x3B
Block Diagram
VCC
SCL RH SDA A1 REF_A RREF 10k 0.5% External Resistor for W option, or 50k 0.5% for U and T options respectively POWER-UP, INTERFACE, EEPROM AND CONTROL LOGIC
RW
RL
REF_B
GND
Pinout
ISL22317 (10 LD TDFN) TOP VIEW
SCL SDA A1 REF_A REF_B 1 2 3 4 5 10 VCC 9 RH 8 RW 7 RL 6 GND
Pin Descriptions
TDFN PIN # 1 2 3 4 5 6 7 8 9 10 SYMBOL SCL SDA A1 REF_A REF_B GND RL RW RH VCC EPAD* DESCRIPTION Open drain I2C interface clock input Open drain Serial data I/O for the I2C interface Device address input for the I2C interface Terminal A for an external reference resistor Terminal B for an external reference resistor Device ground pin "Low" terminal of DCP "Wiper" terminal of DCP "High" terminal of DCP Power supply pin Exposed Die Pad internally connected to GND
*PCB thermal land for QFN/TDFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf
2
FN6912.1 April 15, 2010
ISL22317
Absolute Maximum Ratings
Voltage at any Digital Interface Pin with respect to GND. . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage at any DCP Pin with respect to GND . . . . . . . . . .0V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup (Note 6) . . . . . . . . . . . . . . . . . . Class II, Level B at +125C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Thermal Information
Thermal Resistance (Typical, Notes 4, 5) JA (C/W) JC (C/W) 10 Lead TDFN . . . . . . . . . . . . . . . . . 44 3 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40C to +125C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V VRH-VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V to VCC - 0.3V VRW-VRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V to VCC - 0.3V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. Jedec Class II pulse conditions and failure criterion used. Level B exceptions is using a minimum negative pulse of -0.8V on the A1 pin.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option T option MIN TYP MAX (Note 22) (Note 7) (Note 22) 10 50 100 -3 -4 1 1 TCref 10 VRL + 1 0 0 VCC - 0.3 VCC - 1V +3 +4 UNIT k k k % % ppm/C V V
PARAMETER RH to RL Resistance
RH to RL Resistance Tolerance
U and T options W option
End-to-End Temperature Coefficient VRH VRL RW DCP High Terminal Voltage DCP Low Terminal Voltage Wiper Resistance
All options, match external reference TCr VRH to GND VRL to GND Precision On, RH - floating, VRL = 0V, force IW current to wiper, IW = (VCC - VRL)/RTOTAL Precision Off, RH - floating, VRL = 0V, force IW current to wiper, IW = (VCC - VRL)/RTOTAL
70
RREF
External Reference Resistor
for W option, 0.5% for U option, 0.5% for T option, 0.5%
10 50 50 0.1 0.5
k k k A
ILkgDCP
Leakage on DCP Pins
Voltage at pin from GND to VCC
VOLTAGE DIVIDER MODE (0V @ RL; VCC -0.3V @ RH; measured at RW, unloaded) INL (Note 12) DNL (Note 11) Integral Non-linearity Differential Non-linearity W, U or T option VRL + 0.3V < VRW < VCC - 0.3V W, U or T option VRL + 0.3V < VRW < VCC - 0.3V -0.5 -0.5 0.1 0.1 0.5 0.5 LSB (Note 8) LSB (Note 8)
3
FN6912.1 April 15, 2010
ISL22317
Analog Specifications
SYMBOL ZSerror (Note 9) FSerror (Note 10) Over recommended operating conditions unless otherwise stated. (Continued) TEST CONDITIONS W, U or T option VRL < VRW < VRL + 0.3V W, U or T option VCC - 0.3V < VRW < VCC Match to external Rref, DCP register set between 15 hex and 7F hex Wiper at midpoint (40hex) W option (10k) Wiper at midpoint (40hex) U option (50k) Wiper at midpoint (40hex) T option (100k) RESISTOR MODE (Measurements between RW and RL with RH not connected) RINL (Note 17) RDNL (Note 16) Roffset (Note 15) Integral Non-linearity W, U or T option Current forced to the wiper IW = (VCC - VRL)/RTOTAL (Note 20) W, U or T option Current forced to the wiper IW = (VCC - VRL)/RTOTAL (Note 20) W, U or T option, wiper is out of recommended operation conditions Match to external Rref, DCP register set between 15 hex and 7F hex, all options -3 1 3 MI (Note 14) MI (Note 14) MI (Note 14) ppm/C -2 MIN TYP MAX (Note 22) (Note 7) (Note 22) 0.5 -0.5 TCref 10 1 1 1 2 UNIT LSB (Note 8) LSB (Note 8) ppm/C kHz kHz kHz
PARAMETER Zero-scale Error Full-scale Error
TCV Ratiometric Temperature Coefficient (Notes 13, 19) fcutoff (Note 19) -3dB Cut Off Frequency
Differential Non-linearity
-3
1
3
Offset
0
1 TCref 10
2
TCR Resistance Temperature Coefficient (Notes 18, 19)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 PARAMETER VCC Supply Current (volatile write/read) TEST CONDITIONS VCC = +5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +2.7V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states), 10k ICC2 VCC Supply Current (non-volatile write/read) VCC = +5.5V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +2.7V, fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) ISB VCC Current (Standby) VCC = +5.5V @ +125C, I2C interface in standby state VCC = +2.7V @ +125C, I2C interface in standby state, 10k ISD ILkgDig tDCP (Note 19) tShdnRec (Note 19) Vpor VCC Current (Shutdown) Leakage Current, at Pins REF_A, REF_B, A1, SDA, and SCL DCP Wiper Response Time DCP Recall Time from Shutdown Mode Power-on Recall Voltage VCC = +5.5V @ +125C, I2C interface in standby state Voltage at pin from GND to VCC SCL falling edge of last bit of DCP data byte to wiper new position SCL falling edge of last bit of ACR data byte to wiper stored position and RH connection Minimum VCC at which memory recall occurs 0.2 -0.25 150 150 2.6 50 MIN (Note 22) TYP (Note 7) 0.6 0.35 1.75 1.0 0.5 0.3 0.5 MAX (Note 22) 1.2 0.9 2.5 1.8 1.0 0.75 1.5 0.25 UNIT mA mA mA mA mA mA A A s s V V/ms
VCC Ramp VCC Ramp Rate
4
FN6912.1 April 15, 2010
ISL22317
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tD PARAMETER Power-up Delay TEST CONDITIONS VCC above Vpor, to DCP Initial Value Register recall completed, and I2C Interface in standby state MIN (Note 22) TYP (Note 7) MAX (Note 22) 1 UNIT ms
EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention Temperature T +55C Temperature T +125C tWC (Note 21) Non-volatile Write Cycle Time 1,000,000 50 15 12 20 Cycles Years Years ms
SERIAL INTERFACE SPECS VIL VIH Hysteresis (Note 19) VOL (Note 19) Cpin (Note 19) fSCL tsp tAA tBUF A1, A0, SDA, and SCL Input Buffer LOW Voltage A1, A0, SDA, and SCL Input Buffer HIGH Voltage SDA and SCL Input Buffer Hysteresis SDA Output Buffer LOW Voltage, Sinking 4mA A1, A0, SDA, and SCL Pin Capacitance SCL Frequency Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is and SCL Inputs suppressed SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of VCC, until Valid SDA exits the 30% to 70% of VCC window Time the Bus must be Free Before the SDA crossing 70% of VCC during a STOP Start of a New Transmission condition, to SDA crossing 70% of VCC during the following START condition Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL falling edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window 1300 0.7*VCC 0.05*VCC 0 0.4 10 400 50 900 0.3*VCC V V V V pF kHz ns ns ns
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input Data Hold Time
0
ns
tSU:STO tHD:STO tDH
STOP Condition Setup Time STOP Condition Hold Time for Read, or Volatile Only Write Output Data Hold Time
600 1300 0
ns ns ns
5
FN6912.1 April 15, 2010
ISL22317
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tR (Note 19) tF (Note 19) Cb (Note 19) Rpu (Note 19) tSU:A tHD:A NOTES: 7. Typical values are for TA = +25C and 3.3V supply voltage. 8. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 9. ZSERROR = V(RW)0/LSB. 10. FSerror = [V(RW)127 - VCC]/LSB. 11. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127, where i is the DCP register setting. 12. INL = [V(RW)i - i * LSB - V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 13. TC = --------------------------------------------------------------------------------------------- x ---------------- for i = 15 to 127 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 14. MI = |RW127 - RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 15. ROFFSET = RW0/MI, when measuring between RW and RL. 16. RDNL = (RWi - RWi-1)/MI -1, for i = 1 to 127. 17. RINL = [RWi - (MI * i) - RW0]/MI, for i = 1 to 127. 6 for i = 15 to 127, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) - Min ( Ri ) ] 10 TC R = --------------------------------------------------------------- x ---------------- the minimum value of the resistance over the temperature range. [ Max ( Ri ) + Min ( Ri ) ] 2 +165C 19. Limits should be considered typical and are not production tested. 18. 20. In rheostat mode, if a current is injected into the RW terminal, the magnitude of the current should be such that the developed potential difference between RW and RL terminals is at least 300mV, even at the minimum wiper setting. This ensures that the recommended operating condition of V(RW) V(RL) + 0.3V is satisfied and the part operates in its most accurate resistance. Minimum and Maximum wiper setting can be calculated as follow, MIN code = (0.3V*127)/(Iw*Rtotal), Max code = [(VCC - 0.3V)*127]/(IW*RTOTAL). 21. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-volatile write cycle. PARAMETER SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL SDA and SCL Bus Pull-up Resistor Off-chip A1 Setup Time A1 Hold Time TEST CONDITIONS From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip Maximum is determined by tR and tF For Cb = 400pF, max is about 2k ~ 2.5k For Cb = 40pF, max is about 15k ~ 20k Before START condition After STOP condition MIN (Note 22) 20 + 0.1*Cb 20 + 0.1*Cb 10 1 TYP (Note 7) MAX (Note 22) 250 250 400 UNIT ns ns pF k
600 600
ns ns
22. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
SDA vs SCL Timing
tF tHIGH tLOW tR tsp
SCL tSU:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (OUTPUT TIMING)
tDH
tBUF
6
FN6912.1 April 15, 2010
ISL22317
A1 Pin Timing
START SCL CLK 1 STOP
SDA tSU:A A1 tHD:A
Typical Performance Curves
2 RESISTANCE ERROR (%) RESISTANCE ERROR (%) T = +25C 1 VCC = 2.7V 2 T = +25C 1 VCC = 2.7V
0
0 VCC = 5.5V
-1
VCC = 5.5V
-1
-2
5
25
45 65 85 TAP POSITION (DECIMAL)
105
125
-2
5
25
45
65
85
105
125
TAP POSITION (DECIMAL)
FIGURE 1. RESISTANCE ERROR vs TAP POSITION [I(RW) = VCC/RTOTAL] FOR 100k (T)
FIGURE 2. RESISTANCE ERROR vs TAP POSITION [I(RW) = VCC/RTOTAL] FOR 10k (W)
2 T = +25C 1 RINL (MI) VCC = 5.5V RINL (MI)
2 T = +25C 1 VCC = 5.5V 0
0 VCC = 2.7V
-1
-1
VCC = 2.7V
-2
0
20
40
60
80
100
120
-2
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. INL vs TAP POSITION IN RHEOSTAT MODE FOR 100k (T)
FIGURE 4. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
7
FN6912.1 April 15, 2010
ISL22317 Typical Performance Curves
2 T = +25C 1 RDNL (MI) VCC = 2.7V RDNL (MI) 2 VCC = 2.7V 1
(Continued)
3 T = +25C
0
VCC = 5.5V
-1
VCC = 5.5V
0
-2
0
20
40 60 80 TAP POSITION (DECIMAL)
100
120
-1
0
20
40 60 80 TAP POSITION (DECIMAL)
100
120
FIGURE 5. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 100k (T)
FIGURE 6. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
1.6 RTOTAL ERROR (%) 1.2 0.8 0.4 0.0 -0.4 -40 VCC = 5.5V RTOTAL ERROR (%)
1.0
0.5
VCC = 2.7V
0.0 VCC = 5.5V -0.5
VCC = 2.7V -1.0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 7. RTOTAL ERROR vs TEMPERATURE FOR 100k (T)
FIGURE 8. RTOTAL ERROR vs TEMPERATURE FOR 10k (W)
0.30 T = +25C 0.15 INL (LSB) VCC = 2.7V 0 INL (LSB)
0.30 T = +25C 0.15 VCC = 5.5V 0
-0.15 VCC = 5.5V 0 20 40 60 80 100 120
-0.15
VCC = 2.7V
-0.30
-0.30
0
20
TAP POSITION (DECIMAL)
40 60 80 TAP POSITION (DECIMAL)
100
120
FIGURE 9. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 100k (T)
FIGURE 10. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
8
FN6912.1 April 15, 2010
ISL22317 Typical Performance Curves
0.10 T = +25C 0.05 DNL (LSB) VCC = 2.7V DNL (LSB) 0.05
(Continued)
0.10 T = +25C VCC = 2.7V
0 VCC = 5.5V
0
-0.05
-0.05
VCC = 5.5V
-0.10 0
20
40
60
80
100
120
-0.10
0
20
40
60
80
100
120
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 11. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 100k (T)
FIGURE 12. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0.08
0.4
0.06 ZSERROR (LSB) ZSERROR (LSB)
0.3
VCC = 2.7V
0.04
VCC = 2.7V
0.2 VCC = 5.5V 0.1
0.02 VCC = 5.5V 0 -40 -20 0 20 40 60 80 100 120
0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 13. ZSERROR vs TEMPERATURE FOR 100k (T)
FIGURE 14. ZSERROR vs TEMPERATURE FOR 10k (W)
0 VCC = 5.5V FSERROR (LSB)
0
-0.03 FSERROR (LSB)
-0.3
VCC = 5.5V
-0.06
-0.6
-0.09 VCC = 2.7V -0.12 -40 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
-0.9 VCC = 2.7V -1.2 -40 -20 0 20 40 60 80 100 120
TEMPERATURE (C)
FIGURE 15. FSERROR vs TEMPERATURE FOR 100k (T)
FIGURE 16. FSERROR vs TEMPERATURE FOR 10k (W)
9
FN6912.1 April 15, 2010
ISL22317 Typical Performance Curves
40
(Continued)
40
30 TCr (ppm/ C) TCv (ppm/C)
30 VCC = 2.7V
20
VCC = 2.7V
20
10
VCC = 5.5V
10 VCC = 5.5V
0 15
35
55
75
95
115
0 15
35
TAP POSITION (DECIMAL)
55 75 95 TAP POSITION (DECIMAL)
115
FIGURE 17. TC FOR RHEOSTAT MODE (10k/50k/100k) IN ppm [RREF 2ppm/C]
FIGURE 18. TC FOR VOLTAGE DIVIDER MODE (10k/50k/100k) IN ppm [RREF 10ppm/C]
800 VCC = 5.5V WIPER RESISTANCE () 600 ISB (uA) VCC = 2.7V 400
100 80 T = +125C 60 40 20 0 T = -40C VCC = 5.5V
T = +25C
200
0 -40
0
40 TEMPERATURE (C)
80
120
0
20
40 60 80 TAP POSITION (DECIMAL)
100
120
FIGURE 19. STANDBY ICC vs TEMPERATURE
FIGURE 20. WIPER RESISTANCE vs TAP POSITION WHEN PRECISION IS OFF
Pin Description
Potentiometers Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL22317 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH. With the WR set to 0, the wiper is closest to RL. The voltage potential on the RH terminal must be higher than voltage potential on RL terminal. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. REF_A, REF_B REF_A and REF_B are pins to connect an external resistor. If application is required to connect RL terminal to GND, then the REF_B pin should also be connected to GND. 10
Warning! Do not connect REF_A to GND under any circumstances. That may damage the ISL22317.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. DEVICE ADDRESS (A1) The address input is used to set the A1 bit of the 7-bit I2C interface slave address, see Table 4. A match in the slave address serial data stream must match with the Address input pins in order to initiate communication with the
FN6912.1 April 15, 2010
ISL22317
ISL22317. A maximum of two ISL22317 devices may occupy the I2C serial bus with addresses 50h and 54h.
TABLE 1. MEMORY MAP ADDRESS (hex) 2 1 0 NON-VOLATILE NA Mode Select Register IVR VOLATILE ACR NA WR
Principles of Operation
The ISL22317 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor, is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value.
The non-volatile IVR and volatile WR registers are accessible with the same address 0. The ISL22317 is pre-programed with 40h in the IVR. The Access Control Register (ACR) at address 2 contains information and control bits described below in Table 2. The VOL bit (ACR<7>) determines whether the access is to wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL (MSB) SHDN WIP
0
0
0
0
0 (LSB)
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. While the ISL22317 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the I2C serial interface as described in the following sections.
If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR<6>) disables or enables Shutdown mode. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR<5>) is read only bit. It indicates that non-volatile write operation is in progress. It is impossible to write to the WR or ACR while WIP bit is 1. The Mode Select Bit in Mode Select Register (MSR<7>) at address 1 allows selection of Rheostat or Voltage Divider Mode, see Table 3.
TABLE 3. MODE SELECT REGISTER (MSR) Mode Select
(MSB)
Precision Off
x
x
x
x
x
x (LSB)
When this bit is 0, DCP is in two-terminal Rheostat Mode. In Rheostat Mode, the RH pin should be left unconnected and DCP can be used as variable resistor between RW and RL pins. When this bit is 1, DCP is in three-terminal Voltage Divider Mode. In Voltage Divider Mode, signal is applied between RH and RL terminals. Total resistance between RH and RL terminals is precisely matched to external reference resistor. Refer to reference resistor value in "Analog Specifications" Table on page 3. Default value of Mode Select Bit is 0. The Precision Off bit (MSR<6>) allows the user to turn off the matching mechanism and use the device as a regular,
Memory Description
The ISL22317 contains one non-volatile 8-bit Initial Value Register (IVR), one 8-bit non-volatile Mode Select Register (MSR), and two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). Memory map of ISL22317 is in Table 1. The non-volatile register (IVR) at address 0, contains initial wiper position and the volatile register (WR) contains current wiper position.
11
FN6912.1 April 15, 2010
ISL22317
non-precision DCP by setting this bit to 1. Default value of the Precision Off bit is 0, i.e. matching to external resistor is ON. Note, if the external resistor between REF_A/REF_B is not populated, the DCP will work as a normal DCP without giving 99% precision and with ~40% higher value of the resistance. It is highly recommended to use the bit option (MSR<6>) to turn OFF the precision mode first and then removing the external resistor. All other bits MSR<5:0> are reserved and cannot be written. Any value read from these bits should be ignored. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL22317 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 21). A START condition is ignored during the power-up of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 21). A STOP condition at the end of a read operation, or at the end of a write operation, places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 22). The ISL22317 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL22317 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 01010 as the five MSBs, and the following bit matching the logic value present at pin A1. The LSB is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
Logic value at pin A1
I2C Serial Interface
The ISL22317 supports an I2C bi-directional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL22317 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 21). On power-up of the ISL22317, the SDA pin is in the input mode.
0 (MSB)
1
0
1
0
A1
0
R/W (LSB)
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 21. VALID DATA CHANGES, START, AND STOP CONDITIONS
12
FN6912.1 April 15, 2010
ISL22317
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 22. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE SLAVE
0 1 0 1 0 A1 0 0 A C K
0000 A C K A C K
FIGURE 23. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W=1
A C K
A C K
S AT CO KP
SIGNAL AT SDA
0 1 0 1 0 A1 0 0 A C K
0000 A C K
0 1 0 1 0 A1 0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 24. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL22317 responds with an ACK. At this time, the device enters its standby state (see Figure 23). The non-volatile write cycle starts after a STOP condition is determined and requires up to 20ms delay for the next non-volatile write.
set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL22317 responds with an ACK. Then the ISL22317 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a ACK and STOP condition) following the last bit of the last Data Byte (see Figure 24). In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 24). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit 13
FN6912.1 April 15, 2010
ISL22317
Rheostat Mode Configuration
When DCP is used as a two-terminal variable resistor, the RH terminal should be left unconnected and MSR<7> is 0. Resistance between RW and RL terminal can be calculated by Equation 1:
Rtotal Ri = ----------------- x i 127 (EQ. 1)
Voltage Divider Mode Configuration
In Voltage Divider Mode, voltage or signal is applied between RH and RL terminals and MSR<7> is 1. A potential at RH terminal must be higher than at RL terminal at any time. Total resistance between RH and RL terminal is fixed and matched to external reference resistor. Voltage on the wiper terminal RW can be calculated by Equation 4:
Vrh - Vrl Vrw ( i ) = ----------------------- x i 127 (EQ. 4)
Where i is a decimal code from 0 to 127. Note, that resistance accuracy will decrease at the lowest and the highest taps, where voltage drops < 0.3V. In other words, a minimum and maximum decimal code at which the DCP resistance not exceed 3% precision is as shown in Equations 2 and 3:
0.3 x 127 i ( min ) = ----------------------------------------Iwiper x Rtotal (EQ. 2)
Where i is a decimal code from 0 to 127. Note, that the wiper voltage accuracy will decrease at the lowest and the highest taps, where it is less than 0.3V from ground or from VCC respectively.
Applications Information
In order to get better accuracy in applications where RL pin is connected to GND, it is highly recommended that REF_B pin is also connected to GND. The coupling capacitors of 1F and 0.1F should be placed close to VCC pin.
( Vcc - 0.3 ) x 127 i ( max ) = --------------------------------------------Iwiper x Rtotal
(EQ. 3)
Where Iwiper is a current going through the wiper terminal.
Revision History
DATE 4/6/10 REVISION FN6912.1 CHANGE Page 10 description of Pin A1 references Table 3 changed to Table 4. Page 5, tHD:DAT parameter test condition,"From SCL rising edge ..." changed to "From SCL falling edge ..." Added MSL note to ordering information. Replaced POD to recent version with following changes: 1. Removed mention of "b" from Note 4 since "b" does not exist on the drawing. 2. Added Note 6 callout to lead width on "Bottom View". 3. Corrected the word "indentifier" in Note 6 to read "identifier". Initial Release of Datasheet. Issued FN6912 making it a Rev 0.
5/26/09
FN6912.0
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6912.1 April 15, 2010
ISL22317
Package Outline Drawing
L10.3x3B
10 LEAD THIN DUAL FLAT PACKAGE (TDFN) WITH E-PAD Rev 2, 03/10
3.00 A B 10 2.38 +0.1/ - 0.15 6 PIN 1 INDEX AREA 1 2 0.50 6 PIN #1 INDEX AREA
3.00
6 (4X) TOP VIEW 0.15
1.64 +0.1/ -0.15
4 0.25 +0.05/ - 0.07
BOTTOM VIEW
10x 0.40 +/- 0.1
PACKAGE OUTLINE (10X0.25)
(10x0.20) (10x0.40) SEE DETAIL "X" 0.10 C 0.75 C
2.38
0.05 SIDE VIEW
SEATING PLANE 0.08 C
(8x 0.50)
1.64 TYPICAL RECOMMENDED LAND PATTERN C 0.20 REF 0.05 DETAIL "X" 5
NOTES: 1. 2. 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
15
FN6912.1 April 15, 2010

▲Up To Search▲

Price & Availability of ISL2231710

	To Download ISL2231710 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .